The invention generally relates to a semiconductor device. More particularly, the invention relates to a semiconductor device having a vertical transistor and a method of fabricating the same.
Semiconductor devices such as Dynamic Random Access Memory (DRAM) are becoming more highly integrated. In order to form more transistors in a limited area, a vertical transistor for fabricating a memory cell device in a small area has been proposed. In memory devices, the vertical transistor includes a surrounding gate that surrounds a vertical channel of the gate.
In order to form the surrounding gate in a limited 4F2 area, a channel region is selectively isotropic-etched to make the channel region narrow compared with source/drain regions, thereby obtaining an excellent device characteristic. As a result, the vertical transistor can effectively utilize the limited area. The vertical transistor may be used in various applications requiring small transistors such as DRAM.
The vertical transistor maintains a channel length in spite of reduced device size to provide an effective means to overcome Short Channel Effects (SCE). For example, the surrounding gate can maximize gate controllability to provide an excellent device characteristic of driving current because the surrounding gate has a relatively large current flowing area as well as SCE. Therefore, there is a need for a vertical transistor having a thinner and longer structure.
However, when forming a gate of the vertical transistor with a high aspect ratio, particles may remain on a sidewall or a top surface of a pillar having a high aspect ratio. Since a junction region is formed by an ion implanting process after the gate is formed, there is an insufficient overlap margin between the gate and the junction region. As a result, the body of the vertical transistor is isolated from the semiconductor substrate, which causes a floating body effect.
It is difficult to etch a narrow and deep bit line separation due to the high aspect ratio. Because of the high aspect ratio, there is a possibility that the bit lines will not be separated from each other. It is also difficult to fill an insulating film for bit line separation due to the high aspect ratio. As a result of this phenomenon, the yield of devices might be reduced.